View MAX116XXSPIMB_8509332.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

________________ general description the max115/max116 are high-speed, multichannel,12-bit data-acquisition systems (das) with simultane - ous track/holds (t/hs). these devices contain a 12-bit, 2 s, successive-approximation analog-to-digital con - verter (adc), a +2.5v reference, a buffered reference input, and a bank of four simultaneous-sampling t/hamplifiers that preserve the relative phase information of the sampled inputs. the max115/max116 have two multiplexed inputs for each t/h, allowing a total of eight inputs. in addition, the converter is overvoltage tolerant to ?7v. a fault condition on any channel will not dam- age the ic. available input ranges are ?v (max115) and ?.5v (max116). the parallel interface? data access and bus release timing specifications are compatible with most popular digital signal processors and 16-bit/32-bit microproces- sors. the max115/max116 conversion results can be accessed without resorting to wait-states. ________________________applications multiphase motor controlpower-grid synchronization power-factor monitoring digital signal processing vibration and waveform analysis ____________________________features ? four simultaneous-sampling t/h amplifiers withtwo multiplexed inputs (eight single-ended inputs total) ? 2s conversion time per channel ? throughput: 390ksps (1 channel) 218ksps (2 channels)152ksps (3 channels) 116ksps (4 channels) ? input range: 5v (max115) 2.5v (max116) ? fault-protected input multiplexer (17v) ? internal +2.5v or external reference operation ? programmable on-board sequencer ? high-speed parallel dsp interface ? internal 10mhz clock max115/max116 2x4-channel, simultaneous-sampling 12-bit adcs ________________________________________________________________ maxim integrated products 1 19-1928; rev 0; 1/01 part max115 cax 0? to +70? temp. range pin-package 36 ssop evaluation kit available ordering information max115eax -40? to +85? 36 ssop max116 cax 0? to +70? 36 ssop max116eax -40? to +85? 36 ssop for price, delivery, and to place orders, please contact maxim distribution at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. 3635 34 33 32 31 30 29 2827 26 25 24 23 12 3 4 5 6 7 8 9 1011 12 13 14 agndch3b ch3a ch4b ch4a av ss a1 intconvst rd wr cs clk a0 d6 d7 d8 d9 d10 d11 (msb) agnd refout refin av dd ch1a ch1b ch2a ch2b ssop top view max115max116 2221 20 19 1516 17 18 d3 d0/a2 (lsb)d1/a3 d2 dgnd dv dd d4 d5 pin configuration typical operating circuit a0a1 d0/a2d1/a3 d2d3 d4 d5 d6 d7 d8 d9 d10d11 ch1ach1b ch2a ch2b ch3a ch3b ch4a ch4b max115max116 convst control interface clk refout dgnd agnd refin dv dd 4.7 f 16mhz 0.1 f 0.1 f -5v 0.1 f +5v 0.1 f +5v av ss av dd int cs rd wr downloaded from: http:///
max115/max116 2x4-channel, simultaneous-sampling12-bit adcs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(av dd = +5v ?%, av ss = -5v ?%, dv dd = +5v ?%, v refin = +2.5v (external reference), agnd = dgnd = 0, 4.7? capacitor from refout to agnd, 0.1? capacitor from refin to agnd, f clk = 16mhz, external clock, 50% duty cycle. t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd ...........................................................-0.3v to 6v av ss to agnd ............................................................0.3v to -6v dv dd to dgnd ...........................................................-0.3v to 6v agnd to dgnd .......................................................-0.3v to 0.3v ch_ _ to agnd....................................................................?7v refin, refout to agnd ..........................................-0.3v to 6v digital inputs/outputs to dgnd ..............-0.3v to (dv dd + 0.3v) continuous power dissipation (t a = +70?) 36-pin ssop (derate 11.8mw/? above +70?) ..........941mw operating temperature ranges max115_cax/max116_cax ...............................0? to +70? max115_eax/max116_eax ............................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s)....................................300? conditions units min typ max symbol parameter all channels 12 n resolution bits 0.6 1 inl integral nonlinearity (note 2) lsb max115 ? ?5 bipolar zero error ?0 bipolar zero-error match between all channels mv 25 max115 180 ?/? zero-code tempco ? ?5 mv gain error ?5 max115 25 mv gain error match 120 max115 gain error tempco ?/? snr signal-to-noise ratio db -80 thd (notes 4, 5) total harmonic distortion db 80 sfdr (note 4) spurious-free dynamic range db 80 (note 6) channel-to-channel isolation db lsb 0.6 1 dnl differential nonlinearity 69 (note 4) max116 mv ? ?0 ?8 t a = +25? t a = t min to t max t a = +25? t a = t min to t max max116 90 ? ?0 ?8 max116 t a = +25? t a = t min to t max t a = +25? t a = t min to t max 60 max116 dc accuracy (note 1) dynamic performance (f clk = 16mhz, f in = 10.06khz) (notes 1, 3) downloaded from: http:///
max115/max116 2x4-channel, simultaneous-sampling 12-bit adcs _______________________________________________________________________________________ 3 electrical characteristics (continued)(av dd = +5v ?%, av ss = -5v ?%, dv dd = +5v ?%, v refin = +2.5v (external reference), agnd = dgnd = 0, 4.7? capacitor from refout to agnd, 0.1? capacitor from refin to agnd, f clk = 16mhz, external clock, 50% duty cycle. t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) conditions units min typ max symbol parameter max115 v ? v in input voltage range max115 (-5v to +5v range) ? ?25 i in input current pf 16 c in input capacitance ns 600 t acq acquisition time mhz 10 small-signal bandwidth mhz 1.3 full-power bandwidth mv/ms 2 drop rate ns 10 aperture delay ps 30 aperture jitter ps 500 aperture-delay matching t a = +25? v 2.462 2.5 2.532 v refout output voltage 0 < i ref < 1ma mv/ma 0.5 external load regulation (note 8) ppm/? 30 refout tempco ? 0.1 external capacitive bypass at refin v 2.40 2.50 2.60 input voltage range ? 4.7 22 external capacitive bypass at refout ? ?0 input current k 10 input resistance (note 9) pf 10 input capacitance mhz 16 external clock frequency v 2.4 v ih input high voltage v 0.8 v il input low voltage convst , rd , wr , cs , clk ? pf 15 c in input capacitance a0?3 ? ?0 i in input current max116 ?.5 max116 (-2.5v to +2.5v range) ?5 mhz 5.6 10 14.8 internal clock frequency analog input track/hold reference output (note 7) reference input external clock digital inputs ( convst , rd, wr , cs , clk, a0?3) (note 1) internal clock downloaded from: http:///
max115/max116 2x4-channel, simultaneous-sampling12-bit adcs 4 _______________________________________________________________________________________ conditions units min typ max symbol parameter i out = 1ma v 4 v oh output high voltage i out = -1.6ma v 0.4 v ol output low voltage d0?11 ? ?0 three-state leakage current pf 10 three-state outputcapacitance v 4.75 5 5.25 av dd positive supply voltage v -5.25 -5 -4.75 av ss negative supply voltage v 4.75 5 5.25 dv dd digital supply voltage ma 17 25 i avdd positive supply current ma -20 -15 i avss negative supply current ma 36 digital supply current ? 1 shutdown positive current ? -1 shutdown negative current ? 13 shutdown digital current (note 10) lsb ? psrr+ positive supply rejection (note 10) lsb ? psrr- negative supply rejection (note 11) mw 175 power dissipation digital outputs (d0?11, int ) power requirements electrical characteristics (continued)(av dd = +5v ?%, av ss = -5v ?%, dv dd = +5v ?%, v refin = +2.5v (external reference), agnd = dgnd = 0, 4.7? capacitor from refout to agnd, 0.1? capacitor from refin to agnd, f clk = 16mhz, external clock, 50% duty cycle. t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) timing characteristics(see figure 4, av dd = +5v, av ss = -5v, dv dd = +5v, agnd = dgnd = 0, t a = t min to t max , typical values are at t a = +25?, unless otherwise noted.) guaranteed by design ns 0 t cws cs to wr setup time guaranteed by design ns 0 t cwh cs to wr hold time ns 30 t wr wr low pulse width ns 30 conditions t as address setup time ns 0 t ah address hold time 25pf load ns 55 t id rd to int delay ns 45 t rd delay time between reads guaranteed by design ns 0 t crs cs to rd setup time guaranteed by design ns 0 t crh cs to rd hold time ns 30 t rd rd low pulse width 25pf load (note 12) ns 40 t da data-access time 25pf load (note 13) ns 54 5 t dh bus-relinquish time ns 30 t cw convst pulse width units min typ max symbol parameter downloaded from: http:///
max115/max116 2x4-channel, simultaneous-sampling 12-bit adcs _______________________________________________________________________________________ 5 conditions units min typ max symbol parameter timing characteristics (continued)(see figure 4, av dd = +5v, av ss = -5v, dv dd = +5v, agnd = dgnd = 0, t a = t min to t max , typical values are at t a = +25?, unless otherwise noted.) mode 1, c hannel 1 ? 2 mode 2, c hannel 2 4 mode 3, c hannel 3 6 mode 4, c hannel 4 8 t conv exiting shutdown ms 20 startup time note 1: av dd = +5v, av ss = -5v, dv dd = +5v, v refin = 2.500v (external), v in = ?v (max115) or ?.5v (max116). note 2: integral nonlinearity is the analog value? deviation at any code from its theoretical value after the full-scale range and offset have been calibrated. note 3: clk synchronized with convst . note 4: f in = 10.06khz, v in = ?v (max115) or ?.5v (max116). note 5: first five harmonics. note 6: all inputs except ch1a driven with ?v (max115) or ?.5v (max116) 10.06khz signal, ch1a connected to agnd and digi-tized. note 7: av dd = dv dd = +5v, av ss = -5v, v in = 0v (all channels). note 8: temperature drift is defined as the change in output voltage from +25? to t min or t max . it is calculated as tc = [ ? refout/refout] / ? t. note 9: see figure 2. note 10: defined as the change in positive full scale caused by a ?% variation in the nominal supply voltage. tested with one inputat full scale and all others at agnd. v refin = +2.5v (internal). note 11: tested with all inputs connected to agnd. v refin = +2.5v (internal). note 12: the data access time is defined as the time required for an output to cross +0.8v or +2.0v. it is measured using the circuitof figure 1. the measured number is then extrapolated back to determine the value with a 25pf load. note 13: the bus relinquish time is derived from the measured time taken for the data outputs to change +0.5v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging and discharging the 120pf capacitor. the time given is the part? true bus relinquish time, which is independent of the external bus loading capac- itance. conversion time mode 1, c hannel 1 ksps 390 conversion rate mode 2, c hannel 2 218 mode 3, c hannel 3 152 mode 4, c hannel 4 116 downloaded from: http:///
_______________ detailed description the max115/max116 use a successive-approximationconversion technique and four simultaneous-sampling track/hold (t/h) amplifiers to convert analog signals into 12-bit digital outputs. each t/h has two multiplexed inputs, allowing a total of eight inputs. each t/h output is converted and stored in memory to be accessed sequentially by the parallel interface with successive read cycles. the max115/max116 internal micro- sequencer can be programmed to digitize one, two, three, or four inputs sampled simultaneously from either of the two banks of four inputs (figure 2). the max115/max116 can operate with either an external or internal clock. for internal operation, connect clk to dv dd . max115/max116 2x4-channel, simultaneous-sampling12-bit adcs 6 _______________________________________________________________________________________ ______________________________________________________________pin description figure 1. load circuit for access time and bus relinquish time to output pin 120pf 1.0ma 1.6ma 1.6v channel 3 multiplexed inputs (single-ended) ch3a, ch3b 34, 35 channel 4 multiplexed inputs (single-ended) ch4a, ch4b 32, 33 analog supply voltage av ss 31 interrupt output. falling edge indicates the end of a conversion sequence. int 30 conversion-start input. rising edge initiates sampling and conversion sequence. convst 29 read input (active-low) rd 28 write input (active-low) wr 27 digital ground dgnd 18 data bits d3, d2 19, 20 bidirectional data bits/address bits d1/a3, d0/a2 21, 22 clock input (duty cycle must be 30% to 70%). connect clk to dv dd to activate internal clock. clk 25 chip-select input (active-low) cs 26 reference-buffer output. bypass with a 4.7? capacitor to agnd. refout 7 analog ground. both pins must be connected to ground. agnd 8, 36 data bits. d11 = msb. d11?4 916 digital supply voltage dv dd 17 external reference input/internal reference output. bypass with a 0.1? capacitor to agnd. refin 6 analog supply voltage av dd 5 pin channel 1 multiplexed inputs (single-ended) ch1b, ch1a 3, 4 channel 2 multiplexed inputs (single-ended) ch2b, ch2a 1, 2 function name address bits a1, a0 23, 24 downloaded from: http:///
max115/max116 2x4-channel, simultaneous-sampling 12-bit adcs _______________________________________________________________________________________ 7 mux 2.50v bandgap reference refin 10k agnd refout mux t/ht/h t/h t/h ab mux ab mux ab mux ch1ach1b ch2a ch2b ch3a ch3b ch4a ch4b ab 12-bit dac control logic bus interface clk convst int cs rd wr dv dd dgnd sar 4x12 ram v ref three-state output drivers av dd agnd av ss d0/a2d1/a3 d2 a0a1 d3 d11 (msb) max115max116 v ref comp 10mhz clock figure 2. functional diagram downloaded from: http:///
max115/max116 2x4-channel, simultaneous-sampling12-bit adcs 8 _______________________________________________________________________________________ the conversion timing and control sequences arederived from either an internal clock or an external clock, the convst signal, and the programmed mode. the t/h amplifiers hold the input voltages at the convst rising edge. additional convst pulses are ignored until the last conversion for the sample is com-plete. an on-board sequencer converts one to four channels per convst pulse. in the default mode, one t/h output (ch1a) is converted. an interrupt signal( int ) is provided after the last conversion is complete. convert two to four channels by reprogramming themax115/max116 through the bidirectional parallel interface. once programmed, the max115/max116 continues to convert the specified number of channels per convst pulse until they are reprogrammed. the channels are converted sequentially, beginning withch1. the int signal always follows the end of the last conversion in a conversion sequence. the adc con-verts each assigned channel in 2? and stores the result in an internal 4 x 12-bit memory. at the end of the last conversion, int goes low and the t/h amplifiers begin to track the inputs again. the datacan be accessed by applying successive pulses to the rd pin. successive reads access data words sequen- tially. the memory is not random-access and data fromch1 is always read first. after performing four consecu- tive reads or initiating a new conversion, the address pointer selects ch1 again. additional read pulses cycle through the data words. cs can be held low during successive reads. input bandwidth the t/h? input tracking circuitry has a 10mhz small-signal bandwidth, so it is possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high- frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. analog input range and input protection the max115? input range is ?v, and the max116?input range is ?.5v. the input resistance for the max115 is 10k (typ), and the input resistance for the max116 is 1m (typ). an input protection structure allows input voltages to ?7v without harming the ic.this protection is also active in shutdown mode. s1a s2a hold buffer track c hold 7pf hold from microsequencer refout track mux dac sar s1b s2b s3b s3a c in r3 r2 r1 c in r3 r2 r1 ch_ach_b max115 max116 max115: r1 = , r2 = r3 = 5k max116: r1 = r2 = 5k , r3 = figure 3. equivalent input circuit downloaded from: http:///
track/holds the max115/max116 feature four simultaneous t/hs.each t/h has two multiplexed inputs. a t-switch input configuration provides excellent hold-mode isolation. allow 600ns acquisition time for 12-bit accuracy. the t/h aperture delay is typically 10ns. the 500ps aperture-delay mismatch between the t/hs allows the relative phase information of up to four different inputs to be preserved. figure 3 shows the equivalent input circuit, illustrating the adc? sampling architecture. only one of four t/h stages with its two multiplexed inputs (ch_a and ch_b) is shown. all switches are in track configuration for channel a. an internal buffer charges the hold capacitor to minimize the required acquisition time between conversions. the analog inputappears as a 10k resistor in parallel with a 16pf capacitor for the max115 and as a 1m resistor in par- allel with a 16pf capacitor for the max116.between conversions, the buffer input is connected to channel 1 of the selected track/hold bank. when a channel is not selected, switches s1, s2, and s3 are placed in hold mode to improve channel-to-channel isolation. digital interface input data (a0?3) and output data (d0?11) are multi-plexed on a three-state bidirectional interface. this par- allel i/o can easily be interfaced with a microprocessor (?) or dsp. cs , wr , and rd control the write and read operations. cs is the standard chip-select signal, which enables the controller to address the max115/max116as an i/o port. when cs is high, it disables the wr and rd inputs and forces the interface into a high-z state. figure 4 details the interface timing. programming modes the max115/max116 have eight conversion modes plus power-down, which are programmed through a bidirectional parallel interface. at power-up, the devices default to the input mux a/single-channel conversion mode. the user can select between two banks (mux inputs a or mux inputs b) of four simultaneous-sampled input channels, as illustrated in figure 2. an internal microsequencer can be programmed to convert one to four channels of the selected bank per sample. for a single-channel conversion, ch1 is digitized, and then int goes low to indicate completion of the conversion. max115/max116 2x4-channel, simultaneous-sampling 12-bit adcs _______________________________________________________________________________________ 9 ch1 ch2 ch3 ch4 t acq t conv t ah t as t wr t cwh t dh t da t rd t crs t crh t rd t id t cws convst int cs wr data t cw data in rd figure 4. timing diagram figure 5. programming a four-channel conversion, input mux a a0 (lsb) wr cs a1a2 a3 downloaded from: http:///
max115/max116 for multichannel conversions, int goes low after the last channel has been digitized. to input data into the max115/max116, pull cs low, program the bidirectional pins a0?3 (table 1), andpulse wr low. data is latched into the devices on the wr or cs rising edge. the adc is now ready to convert. once programmed, the adc continues operating in thesame mode until reprogrammed or until power is removed. figure 5 shows an example of programming a four-channel conversion using input mux a. starting a conversion after programming the max115/max116 as outlined inthe programming modes section, pulse convst low to initiate a conversion sequence. the analog inputs aresampled at the convst rising edge. do not start a new conversion while the conversion is in progress.monitor the int output. a falling edge indicates the end of a conversion sequence. reading a conversion digitized data from up to four channels is stored inmemory to be read out through the parallel interface. after receiving an int signal, the user can access up to four conversion results by performing up to four readoperations. with cs low, the conversion results from ch1_ are accessed, and int is reset high on the first rd falling edge. on the rd rising edge, the internal address pointer is advanced. if a single conversion is pro-grammed, only one rd pulse is required. for multi- channel conversions, up to four rd falling edges sequentially access the data for channels 1 through 4.for any number of channels converted, the address pointer is reset to ch1_ after four rd pulses. the address pointer also resets after receiving a cnvst pulse. do not perform a read operation during conver-sion; it will corrupt the conversion? accuracy. __________applications information clock the max115/max116 have an internal 10mhz (typ)clock, which is activated by connecting clk to dv dd (internal clock startup time is 165? typ). the clk inputalso accepts an external clock with duty cycle between 30% and 70%. 2x4-channel, simultaneous-sampling12-bit adcs 10 ______________________________________________________________________________________ x = don? care table 1. modes of operation to dac refin 10k 0.1 f 4.7 f a v = 1 2.5v refout 7 6 (2.5v)(2.5v) max115max116 figure 6. internal reference input mux a/single-channel conversion (default at power-up) power-down x x x 1 input mux b/four-channel conversion 8 1 1 1 0 input mux b/three-channel conversion 6 0 1 1 0 input mux b/two-channel conversion 4 1 0 1 0 input mux b/single-channel conversion 2 0 0 1 0 input mux a/four-channel conversion input mux a/three-channel conversion input mux a/two-channel conversion mode 8 6 4 2 conversion time (s) 1 0 1 0 a0 1 0 0 1 0 0 0 0 0 0 0 0 a1 a2 a3 downloaded from: http:///
internal and external reference the max115/max116 can be used with an internal orexternal reference voltage. an external +2.5 reference can be connected directly at refin. an internal buffer with a gain of +1 provides +2.5v at refout. internal reference the full-scale range with the internal reference is 5v for the max115 and ?.5v for the max116. bypassrefin with a 0.1? capacitor to agnd, and bypass the refout pin with a 4.7? (min) capacitor to agnd (figure 6). the maximum value to compensate the ref- erence buffer is 22?. larger values are acceptable if low-esr capacitors are used. external reference for operation over a wide temperature range, an exter-nal +2.5v reference with tighter specifications improves accuracy. the max6325 is an excellent choice to match the max115/max116 accuracy over the commercial and extended temperature ranges with a 1ppm/? (max) temperature drift. connect an external reference at refin as shown in figure 7. the minimum impedance is 7k for dc currents in both normal oper- ation and shutdown. bypass refout with a 4.7? low-esr capacitor. power-on reset when power is first applied, the internal power-on reset(por) circuitry activates the max115/max116 with int = high, ready to convert. the default conversion mode is input mux a/single channel conversion. see the programming modes section if other configurations are desired. after the power supplies have been stabilized, the reset time is 5?. no conversions should be performed during this phase. at power-up, data-in memory is undefined. software power-down software power-down is activated by setting bit a3 ofthe control word high (table 1). it is asserted after the wr or cs rising edge, at which point the adc immedi- ately powers down to a low quiescent-current state.i avdd and i avss drop to less than 1? (typ), and i dvdd drops to 13? (typ). the adc circuitry and referencebuffer are turned off, but the digital interface and the reference remain active for fast power-up recovery. wake up the max115/max116 by writing a control word (a0?3, table 1). the bidirectional interface inter- prets a logic zero at a3 as the start signal, and powers up in the mode selected by a0, a1, and a2. the refer- ence buffer? settling time and the bypass capacitor? value dominate the power-up delay. with the recom- mended 4.7? at refout, the power-up delay is typi- cally 20ms. transfer function the max115/max116 have bipolar input ranges. figure8 shows the bipolar/output transfer function. code tran- sitions occur at successive-integer least significant bit max115/max116 2x4-channel, simultaneous-sampling 12-bit adcs ______________________________________________________________________________________ 11 to dac refin 10k 4.7 f a v = 1 2.5v refout 7 6 (2.5v) (2.5v) out max6325 max115max116 figure 7. external reference 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 - fs zero input voltage (lsb) output code +fs - 1lsb 4096 max115: fs = 2 x v refout , 1lsb = 4v refout max116: fs = v refout , 1lsb = 2v refout 4096 figure 8. bipolar transfer function downloaded from: http:///
max115/max116 (lsb) values. output coding is two-complement binarywith 1lsb = 2.44mv for the max115 and 1lsb = 1.22mv for the max116. output demultiplexer an output demultiplexer circuit is useful for isolatingdata from one channel in a four-channel conversion sequence. figure 9? circuit uses the external 16mhz clock and the int signal to generate four rd pulses and a latch clock to save data from the desired chan-nel. cs must be low during the four rd pulses. the channel is selected with the binary coding of twoswitches. a 16-bit 16373 latch simplifies layout. motor-control applications vector motor control requires monitoring of the individ-ual phase currents. in their most basic application, the max115/max116 simultaneously sample two currents (ch1a and ch2a, figure 10) and preserve the neces- sary relative phase information. only two of the three phase currents have to be digitized because the third component can be mathematically derived with a coor- dinate transformation. the circuit of figure 10 shows a typical vector motor- control application using all available inputs of the max115/max116. ch1a and ch2a are connected to two isolated hall-effect current sensors and are a 2x4-channel, simultaneous-sampling12-bit adcs 12 ______________________________________________________________________________________ pre clr hc161 1/2 hc74 v cc v cc v cc enp entload a b c d (lsb) 0 12 3 rco dq q clr p0p1 p2 p3 p4 p5 p6 p7 hc688 p = q q0q1 q2 v cc q3 q4q5 q6 q7 g latchclock (to 16373 latch) 0 ch1 0 1 ch2 0 0 ch3 1 1 ch4 1 10k external clock external clock rd int figure 9. output demultiplexer circuit downloaded from: http:///
max115/max116 2x4-channel, simultaneous-sampling 12-bit adcs ______________________________________________________________________________________ 13 part of the current (torque) feedback loop. the max115/max116 digitize the currents and deliver rawdata to the following dsp and controller stages, where the vector processing takes place. sensorless vector control uses a computer model for the motor and an algorithm to split each output current into its magnetiz- ing (stator current) and torque-producing (rotor current) components. if a two-to-three phase conversion is not practical, three currents can be sampled simultaneously with the addition of a third sensor (not shown). optional voltage (position) feedback can be derived by measuring two phase voltages (ch3a, ch4a). typically, an isolated differential amplifier is used between the motor and the max115/max116. again, the third phase voltage can be derived from the magnitude (phase voltage) and its relative phase. for optimum speed control and good load regulation close to zero speed, additional velocity and position feedback are derived from an encoder or resolver and brought to the max115/max116 at ch4b. the addi- tional channels can be used to evaluate slower analoginputs, such as the main dc bus voltage (ch2b), tem- perature sensors (ch3b), or other analog inputs (aux, ch1b). power-supply bypassing and ground management for optimum system performance, use printed circuitboards with separate analog and digital ground planes. wire-wrapped boards are not recommended. connect the two ground planes together at the low-impedance power-supply source. for the best ground connection, connect the dgnd and agnd pins together and con- nect that point to the system analog ground plane to avoid interference from other digital noise sources. if dgnd is connected to the system digital ground, digi- tal noise may get through to the adc? analog portion. the agnd pins must be connected directly to a low- impedance ground plane. extra impedance between the pins and the ground plane increases crosstalk and degrades inl. main dc 12 bit adc + micro- sequencer ch1ch2 ch3 ch4 ab a b temp ab a b aux main dc current/torque feedback voltage/position feedback velocity feedback ac motor simultaneous t/h max115max116 ac motor r/e resolver/ encoder c dsp 12 buffer power stage controller external setpoints figure 10. vector motor control downloaded from: http:///
max115/max116 2x4-channel, simultaneous-sampling12-bit adcs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. ________________________________________________________package information ssop.eps bypass av dd and av ss with 0.1? ceramic capacitors to agnd. mount them with short leads close to thedevice. ferrite beads may also be used to further iso- late the analog and digital power supplies. bypass dv dd with a 0.1? ceramic capacitor to dgnd. chip information transistor count: 4116substrate connected to av ss process: bicmos downloaded from: http:///

▲Up To Search▲

Price & Availability of MAX116XXSPIMB

	To Download MAX116XXSPIMB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .